Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder
DOI:
https://doi.org/10.54654/isj.v9i01.36Keywords:
NB-LDPC, Basic-set, Trellis min-max, VLSI design.Tóm tắt
Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.
Tóm tắt— Các mã LDPC phi nhị phân (NB-LDPC) vượt trội so với các mã LDPC nhị phân về chất lượng sửa lỗi và thuộc tính lỗi san bằng khi chiều dài là trung bình. Tuy nhiên, nhược điểm của các bộ giải mã NB-LDPC là tính phức tạp cao và độ phức tạp tăng đáng kể khi bậc của trường Galois cao. Trong bài báo này, thuật toán Trellis Min-Max dựa trên tập cơ sở được đơn giản hóa được đề xuất cho xử lý nốt biến mà hiệu quả cho các trường Galois bậc cao để giảm độ phức tạp của khối nốt biến (VNU) cũng như cả bộ giải mã. Kiến trúc bộ giải mã tương ứng với thuật toán đề xuất được thiết kế cho mã NB-LDPC (837, 726) thông qua trường GF(32). Các kết quả thực hiện sử dụng công nghệ CMOS 90-nm chỉ ra rằng kiến trúc bộ giải mã được đề xuất giảm số lượng cổng logic 21,35% và 9,4% với chất lượng sửa lỗi gần như không thay đổi so với các nghiên cứu gần đây.
Downloads
References
[1]. H. C. Davey and D. J. MacKay, “Low-density parity check codes over GF(q),” in Information Theory Workshop, pp. 165-167, Jun. 1998.
[2]. R. Peng and R.-R. Chen, “WLC45-2: Application of nonbinary LDPC codes for communication over fading channels using higher order modulations,” in IEEE Global Telecommunications Conference (GLOBE-COM’06), pp. 1-5, Dec. 2006.
[3]. M. Arabaci, I. B. Djordjevic, L. Xu, and T. Wang, “Nonbinary LDPCcoded modulation for high-speed optical fiber communication without bandwidth expansion,” IEEE Photonics Journal, vol. 4, no. 3, pp. 728-734, Jun. 2012.
[4]. C. A. Aslam, Y. L. Guan, and K. Cai, “Non-binary LDPC code with multiple memory reads for multi-level-cell (MLC) flash,” in Asia-Pacific Signal and Information Processing Association, Annual Summit and Conference (APSIPA), pp. 1-9, 2014.
[5]. D. Declercq and M. Fossorier, “Decoding algorithms for nonbinary LDPC codes over GF(q),” IEEE Trans. Commun., vol. 55, no. 4, pp.633-643, Apr. 2007.
[6]. V. Savin, “Min-max decoding for non binary LDPC codes,” in in Proc. IEEE Int. Symp Inf. Theory, Toronto, ON, Canada, pp. 960-964, Jul. 2008.
[7]. X. Zhang and F. Cai, “Reduced-complexity decoder architecture for nonbinary LDPC codes,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 19, no. 7, pp. 1229-1238, 2011.
[8]. K. He, J. Sha, and Z. Wang, “Nonbinary LDPC code decoder architecture with efficient check node processing,” IEEE Trans. Circuits Syst. II, Express Briefs, vol. 59, no. 6, pp. 381-385, 2012.
[9]. F. Cai and X. Zhang, “Relaxed min-max decoder architectures for nonbinary low-density parity-check codes,” , IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 21, no. 11, pp. 2010-2023, Nov. 2013.
[10]. J. O. Lacruz, F. Garc´ıa-Herrero, D. Declercq, and J. Valls, “Simplified trellis min-max decoder architecture for nonbinary low-density paritycheck codes,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 23, no. 9, pp. 1783-1792, Sep. 2015.
[11]. J. O. Lacruz, F. Garc´ıa-Herrero, J. Valls, and D. Declercq, “One minimum only trellis decoder for non-binary low-density parity-check codes,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp. 177-184, Jan. 2015.
[12]. H. P. Thi and H. Lee, “Two-extra-column trellis min–max decoder architecture for nonbinary LDPC codes,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 25, no. 5, pp. 1787-1791, May. 2017.
[13]. J. O. Lacruz, F. Garcia-Herrero, M. J. Canet, J. Valls, and A. P´erez-Pascual, “A 630 Mbps non-binary LDPC decoder for FPGA,” in Circuits and Systems (ISCAS), 2015 IEEE International Symposium, pp.1989-1992, 2015.
[14]. J. O. Lacruz, F. Garc´ıa-Herrero, M. J. Canet, and J. Valls, “Highperformance NB-LDPC decoder with reduction of message exchange,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 24, no. 5, pp. 1950-1961, May. 2016.
[15]. J. O. Lacruz, F. Garca-Herrero, M. J. Canet, and J. Valls, “Reducedcomplexity nonbinary LDPC decoder for high-order galois fields based on trellis min–max algorithm,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 24, no. 8, pp. 2643-2653, Aug. 2016.
[16]. H. P. Thi and H. Lee, “Basic-set trellis min–max decoder architecture for nonbinary ldpc codes with high-order galois fields,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 496-507, 2018.
[17]. J. O. Lacruz, F. Garc´ıa-Herrero, and J. Valls, “Reduction of complexity for nonbinary LDPC decoders with compressed messages,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 23, no. 11, pp. 2676-2679, Nov. 2015.
[18]. B. Zhou, J. Kang, S. Song, S. Lin, K. Abdel-Ghaffar, and M. Xu, “Construction of non-binary quasi-cyclic LDPC codes by arrays and array dispersions,” IEEE Trans. Commun., vol. 57, no. 6, pp. 1652-1662, Jun. 2009.
Downloads
Published
How to Cite
Issue
Section
License
Proposed Policy for Journals That Offer Open Access
Authors who publish with this journal agree to the following terms:
1. Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
Proposed Policy for Journals That Offer Delayed Open Access
Authors who publish with this journal agree to the following terms:
1. Authors retain copyright and grant the journal right of first publication, with the work [SPECIFY PERIOD OF TIME] after publication simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
