Solution for Cryptographic Intervention in PCI-Express Data Transmission on FPGA Board
DOI:
https://doi.org/10.54654/isj.v2i12.108Keywords:
PCI-Express, FPGA, specialized MH block cipher algorithmTóm tắt
Abstract—With high-speed data transmission such as PCI-Express, the cryptographic intervention in the transmission line, which does not affect the data transmission process but still ensures the data transmission rate of the protocol, will be the foundation to develop cryptographic applications using PCI-Express protocol. In this article, a technical solution to capture the data packet of the PCI-Express protocol using FPGA technology will be presented. Using the standard library of PCI-Express on the computer to connect to the FPGA board, on which organizing the data according to the standard of PCI-Express protocol, at the same time to cryptographic intervening on the line. Thus, plaintext will be transmitted from the computer to the FPGA board via PCI-Express interface, then it will be organized, cryptographic intervened and transmitted back to the computer.
Tóm tắt—Với đường truyền dữ liệu tốc độ cao như PCI-Express, việc can thiệp mật mã vào trong đường truyền để không ảnh hưởng đến quá trình truyền dữ liệu mà vẫn đảm bảo được tốc độ truyền dữ liệu của giao thức mang lại sẽ là cơ sở để phát triển các ứng dụng mật mã sử dụng giao thức PCI-Express. Trong bài báo này sẽ trình bày một giải pháp kỹ thuật bắt gói tin dữ liệu của giao thức PCI-Express sử dụng công nghệ FPGA. Sử dụng bộ thư viện chuẩn PCI-Express trên máy tính để thực hiện kết nối tới bo mạch FPGA, qua đó trên FPGA thực hiện tổ chức dữ liệu theo chuẩn giao thức PCI-Express, đồng thời tổ chức can thiệp mật mã trên đường truyền. Như vậy, dữ liệu rõ sẽ được truyền từ máy tính xuống bo mạch FPGA thông qua giao tiếp PCI-Express, sau đó được tổ chức, can thiệp mật mã và truyền lại cho máy tính.
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References
Intel, “DE4 PCIe Qsys example designs”, February 2, 2018.
Intel, “PCI-Express high performance reference design”, 2014.
PCI-SIG, “PCI Express Base Specification Revision 2.01”, March 4, 2009.
Intel, “IP Compiler for PCI Express user guide”, August 2014.
Altera Corp (2016), “DE4 User manual”. url: ftp://ftp.altera.com/up/pub/Altera_Material/Boards/DE4/DE4_User_Manual.pdf
Ankita R. Tembhare, Dr.Pramod B. Patil, “Design & Implementation of PCI Express BUS Physical layer using VHDL”, IRITCC July 2014, Vl.2 Issue 7.
Kun Cheng, Weiyue Liu, Qi Shen, Shengkai Liao, “Design and Implementation of High-throughput PCIe with DMA Architecture between FPGA and PowerPC”, Journal of IEEE Transactions on Nuclear Science, 2018.
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