Speeding up data processing on firewall using FPGA
DOI:
https://doi.org/10.54654/isj.v1i21.1035Keywords:
FPGA, data processing, firewall based on FPGA, speeding up processing using FPGATóm tắt
Abstract— This article focuses on one of the methods to improve the data processing performance of firewalls by taking advantage of the power of FPGA (Field-Programmable Gate Array) chips in analyzing packets at the network layer instead of CPU. FPGA chips provide a flexible and powerful platform for deploying network firewall data processing functions, ranging from IP address filtering, access policy inspection, data classification to virus checking. Additionally, the research team conducted theoretical experimental research on the chip Xilinx XC7A200T, one of the popular and high-performance chip models. The results of this research are the premise for researching and designing a high-speed firewall model using FPGA.
Downloads
References
Enis Karaarslan, Mohammed Babiker (2021). Digital Twin Security Threats and Countermeasures: An Introduction. IEEE.
Y. Permpoontanalarp; C. Rujimethabhas (2002). A graph theoretic model for hardware-based firewalls. IEEE.
Suchart Khummanee; Atipong Khumseela; Somnuk Puangpronpitag. (2013). Towards a new design of firewall: Anomaly elimination and fast verifying of firewall rules. IEEE.
Fatih Ertam, Mustafa Kaya (2018). Classification of firewall log files with multiclass support vector machine. IEEE.
Davison Zvabva, Pavol Zavarsky, Sergey Butakov, John Luswata (2018). Evaluation of Industrial Firewall Performance Issues in Automation and Control Networks. IEEE.
Li, X., Zhang, Y., & Wang, J. (2017). "A New Method of Firewall Optimization Based on Machine Learning." In Proceedings of the 2017 IEEE 2nd Advanced Informatzon Technology, Electronic and Automation Control Conference (IAEAC) (pp. 1454-1458). IEEE.
Khan, M. R., Zulkernine, M., & Al-Nashif, Y. (2020). "Network Security Monitoring and Attack Detection: Methods and Techniques." CRC Press. IEEE
Andriotis, P., Korolov, A., & Mavroeidakos, T. (2018). "Firewall Optimization with Genetic Algorithm in Software-Defined Networks." In Proceedings of the 2018 International Conference on Computer and Information Sciences (ICCIS) (pp. 1-5). IEEE.
Shouyi Yin, Shibin Tang, Xinhan Lin, Peng Ouyang, Fengbin Tu (2019). A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA. IEEE.
Mohamed Khalil-Hani; Vishnu P. Nambiar; M. N. Marsono (2010). Hardware Acceleration of OpenSSL Cryptographic Functions for High-Performance Internet Security). IEEE.
Tomoaki Sato, Sorawat Chivapreecha, Phichet Moungnoul, Kohji Higuchi (2017). An FPGA Architecture for ASIC-FPGA Co-design to Streamline Processing of IDSs. IEEE
Raouf Ajami, Anh Dinh (2011). Design a hardware network firewall on FPGA. IEEE
Phan, K.V., Tran, T.V. and La, P.H. 2020. A solution for packet security 1 Gbps on layer 2 with technology FPGA. Journal of Science and Technology on Information security. 8, 2 (Apr. 2020), 19-24. DOI: https://doi.org/10.54654/isj.v8i2.29.
Downloads
Published
How to Cite
Issue
Section
License
Proposed Policy for Journals That Offer Open Access
Authors who publish with this journal agree to the following terms:
1. Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
Proposed Policy for Journals That Offer Delayed Open Access
Authors who publish with this journal agree to the following terms:
1. Authors retain copyright and grant the journal right of first publication, with the work [SPECIFY PERIOD OF TIME] after publication simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
2. Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
3. Authors are permitted and encouraged to post their work online (e.g., in institutional repositories or on their website) prior to and during the submission process, as it can lead to productive exchanges, as well as earlier and greater citation of published work (See The Effect of Open Access).
